1. Field of the Invention
The present invention relates to a novel system for accessing a main memory of a large mainframe computer. More particularly, the present invention relates to an access system that simultaneously processes requests for access to a plurality of memory banks and resolves conflicts between the read and write bus by assigning access time slots to the individual banks during the time when data will be transferred to or from a specific memory bank.
2. Description of the Prior Art
Heretofore, large mainframe processing systems have employed separate read and write paths. Information from a specific port is multiplexed to a requested memory bank of a plurality of banks so as to create a particular and unique path between an I/O port and a specified bank in memory. Similarly, information being accessed from a memory bank has a multiplexed path for each requestor for a read operation from each memory bank so as to create a unique path from a bank in memory to an input/output requestor port. It will be understood that such individual paths permits information to be processed in parallel and that individual paths may be set up in parallel so as to transfer information from different ports to different banks in memory. This system of accessing memory is sometimes referred to as direct I/O muxing of memory banks.
Such systems permits parallel data paths and parallel processing of simultaneous requests. It has been suggested that the complex direct I/O muxing circuitry can be simplified by providing a plurality of read buses, one for each I/O port. This would permit simultaneous processing of requests from different banks of memory but would prevent processing of simultaneous requests from the same bank in memory.
It would be desirable to further simplify the operation of direct I/O muxing by eliminating the complex muxing circuitry and by providing a single read bus and a single write bus for all of the memory banks at a main storage unit and also providing an access system which permits simultaneous overlapping process of requests and unique data transfer times on the read and write bus.